Cadence Q DRIVE SERIES User Manual download pdf (Page 4)

In order to have Synthesis tool read your Verilog files go to the “ac_shell” window, and

type the following:

ac_shell> set top “my_design”

This command assigns “my_design” as the top-level module in your design.

Next, load all the Verilog files into the Synthesis tool. To do this go to the “ac_shell”

window and type the following:

ac_shell> read_verilog my_design.v full_adder.v ff.v mux.v

(d) Generate a netlist:

To generate a netlist corresponding to your Verilog RTL files, type the following on the

“ac_shell” window:

ac_shell> do_build_generic –module my_design

(e) View the schematic of the design:

Once the gate-level netlist is generated then you can view your final schematic.

To view the schematic:

From within the module browser shown in Figure 2, double click the my_design module.

The schematic of my_design will display on the schematic window.

Figure 2

Module Browser

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Cadence Q DRIVE SERIES User Manual Page 4