Cadence Q DRIVE SERIES User Manual download pdf (Page 11)

Appendix A

Verilog RTL files:

(a) The top level-module, my_design.v:

module my_design (bypass0, bypass1, module_clock, rst, a, b, cin, sel, out_sum,

out_cout);

input bypass0, bypass1, module_clock, rst, a, b, cin, sel;

output out_sum, out_cout;

wire wbypass0, wbypass1, wa, wb, wcin, wsel, wout_sum, wout_cout;

ff ff1 (.clk(module_clock), .rst(rst), .d(bypass0), .q(wbypass0));

ff ff2 (.clk(module_clock), .rst(rst), .d(bypass1), .q(wbypass1));

ff ff3 (.clk(module_clock), .rst(rst), .d(a), .q(wa));

ff ff4 (.clk(module_clock), .rst(rst), .d(b), .q(wb));

ff ff5 (.clk(module_clock), .rst(rst), .d(cin), .q(wcin));

ff ff6 (.clk(module_clock), .rst(rst), .d(sel), .q(wsel));

ff ff7 (.clk(module_clock), .rst(rst), .d(wout_sum), .q(out_sum));

ff ff8 (.clk(module_clock), .rst(rst), .d(wout_cout), .q(out_cout));

full_adder fa (.a(wa), .b(wb), .cin(wcin), .sum(wsum), .cout(wcout));

mux mx0 ( .a(wbypass0), .b(wsum), .sel(wsel), .out(wout_sum));

mux mx1 ( .a(wbypass1), .b(wcout), .sel(wsel), .out(wout_cout));

endmodule

(b) full_adder.v:

module full_adder (a, b, cin, sum, cout);

input a, b, cin;

output sum, cout;

wire cout = (a & b) | (cin & (a | b));

wire sum = a ^ b ^ cin;

endmodule

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Cadence Q DRIVE SERIES User Manual Page 11